Performance analysis of low power linear-phase fir filter by reconfigurable applications in cascaded form

In multiplier less FIR filter, tremendous effects came into existence to minimize the adders which are present in the multiplier block, for the sake of reducing total area of chip and consumption of power. If there are less no of adders in the multiplier block then there is no need to reduce the power consumption of power in a finite impulse response circuit. Here comes a power oriented method of optimization in a linear phase finite impulse response filter which is used in this system [1]. In search of discrete coefficient algorithm, we use the power index which has the mean adder depth in structural adders. The existing systems techniques uses transposed form configuration, the drawback are less efficiency and area complexity. Instead of searching for coefficient sets that reduces the adders as traditional algorithm, to find a coefficient set that minimize the AAD addition adder depth of SA's structural adders. By using stable and reconfigurable applications is developed to search for the discrete coefficients. As a result, area complexity reduces with increases performance and high efficiency is obtained [2,3]. XILINX system generator toolbox is required for circuit implementation.