Performance Evaluation of Various Multipliers in Minimization of Registers

This paper describes about the register minimization for the multipliers. In order to reduce the size of the multiplier we are going to use new theory called Galois field theory. An efficient digit-serial systolic array is proposed for multiplication in finite field (2^m) using the standard basis representation. The maximum register required to get the output of the multiplier is 2^m. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation. In this paper we are going to construct the multiplier for different multiplier algorithm using verilog code, and we are going to compare the performance of the different multipliers. Finally all multiplier are going to be implemented in Spartan 3FPGA.