Migration Methodology in MPSoC Based on Performance Analysis via SDF Graph

Multiprocessor Systems-on-Chip (MPSoC) allow the implementation of heterogeneous architectures with a high integration capacity. The MPSoC become capable of implementing complex functionalities and realize mass treatment in real time at low cost. As a consequence, MPSoC present the best alternative for the design of multimedia applications characterized by the complexity of data treatment and heavy constraints. To deal with complexity, modeling at different abstraction levels is necessary.

An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost. Hence, it is advisable to have a method of performance analysis enough early in the MPSoC design flow to determine if a task in a priori software could eventually migrate in hardware. This method of analysis must take into account the constraints described by the application and the target platform.

In this context, we deal with the migration of a software task candidate to be implemented to hardware component. This problem is processed at two abstraction levels (Transaction Accurate level and Cycle Accurate level). To analyze the performance at these abstraction levels, a technical analysis of performance under constraints based on Synchronous Data Flow (SDF) graph is proposed. Experiments on MJPEG decoder are made to illustrate the efficiency of our approach and the proposed technical of performance analysis based on SDF graphs.