Low Power Inverter and Barrel Shifter Design Using Adiabatic Principle

Adiabatic switching technique based on energy recovery principle is one of the innovative solutions at circuit and logic level to achieve reduction in power dissipation. Adder was considered as one of the bench mark circuits by many researchers. Since most of the scientific applications require floating point computations which require barrel shifter as one of the components for hardware implementation and since not much efforts have been reported to be taken by the researchers to minimize its power dissipation, it is proposed to implement barrel shifter using adiabatic logic. A barrel shifter needs nlog2n multiplexers for n-bit shifting. Hence designing a low power MUX for using as a repetitive block in the barrel shifter will considerably reduce the power dissipation in barrel shifter. This paper compares the simulation results for power and delay parameters of basic multiplexer using conventional CMOS approach and adiabatic logic approach. The circuits are designed using cell based approach with 180nm device size. Cadence ASIC tools are used to design and simulate the performance. The outcome of this research work will provide guidelines for designing barrel shifter using low power multiplexers.