Cache-coherent distributed shared memory and their outlooks on its development and future challenges

Multiprocessors were developed using two main architectural approaches in the 1980s. The dominating design for modest numbers of processors (usually fewer than 16 or 32) was a single shared memory with numerous processors linked by a bus. Dispersed shared memory is an architectural concept that uses physically distributed memories to enable multiprocessors to support a single shared address space. For multiprocessors with moderate to large numbers of processors, hardware supported distributed shared memory is becoming the dominant approach. Cache coherence enables such systems to utilize caching to exploit locality in applications without affecting the programmer's memory model. The Stanford DASH multiprocessor, the first functional implementation of hardware-supported scalable cache coherence, is described. We cover the major advances that led to the invention of cache-coherent distributed shared memory. We then provide our take on such designs and explore some of the major technical difficulties that remain.