Modeling systems-on-a-chip at the transaction level in systemc

One of the characteristics of the problem which we are dealing with here is that we control neither the language (SystemC is defined by a consortium on which we have only little influence), nor the execution model (which is part of SystemC).A solution could have been to study the execution model of SystemC, to redefine it in terms of automata or another well-known formalism, and to work directly and only on this formalism. This paper first presents today's design flow, with the different levels of abstraction used to describe a chip. Also, this paper details the Transaction Level Modeling level of abstraction and present the way it is implemented in SystemC.