Enhanced Performance of Fast Fourier Transform (FFT) Based Cardiac System with Modified Compressor using Vedic Algorithm

In Digital Signal Processing, different algorithms are used to perform various functions, out of which Fast Fourier Transform is an important algorithm which is used in linear filtering, spectrum analysis, etc. FFT computation involves (Nlog₂N) multiplication and (N/2 log₂N) addition operations. So multiplier structure plays an important role in FFT processor configuration. In this paper a high speed FFT processor using Vedic mathematics is proposed in which a novel 4: 2, 5: 2 and 7: 2 compressors are used to perform the partial product addition. It is shown that the proposed compressor based multiplier is faster than the existing multiplier. Also it is shown that the FFT processor using this compressor based multiplier achieves less area complexity and High speed computation.