A Simple And Geometry Based Fast Space-Vector Pwm Technique For 15 Level Cascaded Multilevel Inverter With Reduction Of Switches

In this paper proposed a simple Space Vector Pulse Width Modulation (SVPWM) algorithm for medium voltage Multilevel Inverter (MLI) with reduced power semiconductor devices and triggering circuits. The result of its lower switching losses and synthesize the maximum output waveform. Conventional scheme and inverter structure incorporated more computational problem and to implement in hardware with increase of level. A new multilevel inverter and SVPWM scheme is much accurate with fast determination of vector location and dwell time calculation with simpler mathematical calculation. In order to minimize the harmonics, the effective switching state transition of SVPWM is computed and to compare with multi-carrier signals. The complexity of experimental digital implementation is simpler by this scheme. The proposed algorithm is simulated and experimentally results are validated with FPGA SPARTAN 6E. The proposed SVPWM and MLI can be easily extent the higher-level output waveform.