Asian Journal of Research in Social Sciences and Humanities
  • Year: 2016
  • Volume: 6
  • Issue: 12

Low Cost and Efficient Implementation of Sobel Edge Detector

*Associate Professor, Rajalakshmi Engineering College, India

**Professor, College of Engineering, Anna University, Guindy, India

***PG Student, Rajalakshmi Engineering College, India

Online published on 9 December, 2016.

Abstract

It is proposed to employ the Sobel edge detection operator for edge detection of real-time images leading to the extraction of their qualitative information. As an example, this detection technique is applied along with pattern recognition, for direction identification by a wheeled mobile robot (WMR). Both simulation and experimental results are presented. The hardware has been implemented on low cost Spartan 6 LX 9 FPGA with 75 MHz clock frequency, obtaining a processing time of 2.58 ms. In order to further reduce this time, in the competitive real world applications, the Sobel operator is implemented in a distributed manner using parallel architecture. It is shown that the edge detection time is then reduced by four times when compared to frame level implementation, which is especially valuable in embedded system applications employing image processing techniques.

Keywords

Block Level, Edge Detection, Embedded System Applications, Image Processing, Low-Cost FPGA