Efficient Low Power Design of 4-Tap and 6-Tap 2d Daubechies Wavelet Filters using Pipelined Direct Mapping Method

This paper presents an area efficient and low power multidimensional (2D) Daubechies wavelet transform 4-tap (Daub4) and 6-tap (Daub6) with pipelined direct mapping method for image compression. Due to separability property of the multi-dimensional Daubechies, the architecture has been implemented using a cascade of two N-point one-dimensional (1-D) Daub4 and Daub6. The 2-dimensinal discrete wavelet transform lifting scheme algorithm has been implemented using MATLAB program for both modules Forward Daubechies Wavelet Transform (FDWT) and Inverse Daubechies Wavelet Transform (IDWT) to determine the Peak Signal to Noise Ratio (PSNR) and correlation in between retrieved image and input image. The architectures were synthesized by VHDL and implemented on Altera®Cyclone II (EP2C35F672C6) Field Programmable Gate Array (FPGA). Simulation results and analysis of the power consumption, maximum frequency and latency are discussed in this paper.