Design of Low Power and High Performance Phase Locked Loop using Dual Mode Logic

The Phase Locked Loop has wide variety of application such as frequency synthesizers, tracking satellite, and demodulation in telecommunication; it needs to operate with low power. When the static logic is used in PLL, it operates with low power consumption but increases delay. When it operates in dynamic logic it consumes more power but the speed of operation increases. In order to attain both the advantages of static and dynamic logic, Dual Mode Logic method is proposed in the design. In Dual Mode Logic, the circuit operates both in static and dynamic modes of operation. In static mode, saves power and in dynamic mode the performance increases. The simulation is performed with the 180nm CMOS technology and the result shows that the suggested method yields reduced power consumption and computational delay when compared with the CMOS logic.