Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai, India
Online published on 2 July, 2016.
Filters play a vital role in information and communication technology. This project proposes a less complexity FFA based parallel FIR filter design and implementation. This paper proposes the design of fast parallel filter with the block sizes L=2,3 and 4 respectively. By employing parallelism two or more number of samples are processed at each clock cycle which can be effectively used for multirate applications. The number of complex multiplications are reduced by employing polyphase decomposition. Here for all the cases, the overall filter output responses is decomposed in to several sub parts which includes sub filters and adders used before and after filters. The computational complexity is reduced for the fast parallel FIR filter when compared to the conventional parallel FIR filter. The simulation is done in Verilog with cyclone II family and EP2C70F672C6 device and EP2C35F672C6 device. The hardware implementation is done with Altera DE2 board and the results are reported. The results shows that the fast parallel filtering is efficient in terms of computational complexity
FIR filter, Polyphase decomposition, filter coefficients, fast parallel filtering, multiplications and additions
