Assistant Professor, Department of ECE, Info Institute of Engineering, Coimbatore, Tamil Nadu, India
Online published on 2 July, 2016.
Recent trends in mobile computing and multimedia application demand low power digital signal processing systems (DSP). The most important block in any DSP system is a finite impulse response (FIR) filter. Here a reliable low power FIR filter is designed using Vedic multipliers which specifically perform addition and shifting operation. The addition is done using full adder with 9 transistors which use only 3 transistor XOR gate. A four tap FIR filter was implemented in microwind 2 electronic design automation tool using CMOS 90nm technology. In the proposed design the power consumption is reduced by 23% and delay has been reduced by 44% when compared with the existing FIR filters.
Power consumption, Delay, Digital signal processor, CMOS
