*Research Scholar, Department of Information and Communication Engineering, Anna University, Chennai, India
**Professor & Head, Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, India
Online published on 2 July, 2016.
In this paper, a novel transmission gate based 10 transistor (TG 10T) SRAM cell is proposed. Read and write bit lines are decoupled in the proposed cell and single bit line write scheme with loop-cutting is employed in the TG 10T SRAM cell to reduce active power consumption during the write operation. Proposed TG 10T and conventional six transistors (6T) SRAM cells are simulated using TSMC based 90nm CMOS technology. Transmission gate is used at bit line side to improve readability of both =0‘ and =1‘ output and at the word line side to improve write ability of both =0‘ and =1‘. Although the proposed cell incurs area penalty in terms of four transistors (43.39%), the leakage performance of the TG 10T SRAM cell is better for both gate and subthreshold leakage when compared with conventional 6T SRAM cell.
SRAM, CMOS Technology, transmission gate, subthreshold leakage, gate leakage
