Design of Modified Variable-Latency Speculating Booth Multiplier with Carry Skip Adder

Data hazards cause degradation in pipeline performance for data-intensive computing processes. To improve the performance, an efficient modified variable-latency speculating booth multiplier (VLSBM) is proposed, which successively performs a speculating phase and correcting phase. The critical path is reduced by partitioning the modified VLSBM partial products into (n-z)-bit least significant part (LSP) and (n + z)-bit most significant part (MSP). An estimation function predicts the carry to the MSP, which lets independent calculation of the partial product accumulation by parts. The data dependence is masked and the correcting phase is ignored when the carry prediction is accurate, thus having a speed-up in the pipelined datapath. For inaccurate prediction of carry, the speculation phase is flushed and the correcting phase is utilized to produce the exact output. VHDL is used as a description language and a Xilinx ISE SIM as a simulation tool for implementation.