Design and Implementation of Cryptographic Shared Processor using FPGA

The important task in a communication system is to transfer information in a complex network. Offering authentication and integrity of information to the data transmitted is very essential to make secure communication. In this paper, we explore high-speed, cost-effective hardware algorithm using fast FIR algorithm (FFA) for data encryption/decryption. We also propose a reconfigurable shared processor using FFA and BLAKE algorithm providing speed up operations. The NIST nominated BLAKE hash functions as the standard candidate algorithm from the second round SHA-3 contest. The FIR is designed for asymmetric cryptographic system. This proposed shared algorithm imparts the advantages of both the asymmetric and symmetric functions. The coding of the FIR and BLAKE are done in VHDL and the synthesis was done using Modelsim. The results show that the proposed algorithm and its implementation in FPGA are more efficient than the normal hardware.