An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications

Power consumption is the fundamental design constraint in Very Large Scale Integration (VLSI) technology with the improvement in transistor counts and clock frequencies. This paper introduces techniques for originating Static Random Access Memory (SRAM) cell with low power and delay. The proposed 6T SRAM cell uses self-controllable voltage level-upper (SVL-U) method and transmission gate logic with the reduction in dynamic power by 68% on an average related to conventional techniques. The proposed 7T SRAM cell works adiabatic technique which diminishes the dynamic power by 84% on an average compared to conventional techniques. Parameters like delay and power-delay product (PDP) are determined and the simulation is executed using Tanner EDA tool at 250nm, 180nm, and 45nm technologies.