*Assistant Professor, Sri Krishna College of Technology, Kovaipudur, Coimbatore, Tamil Nadu, India
**Professor & Head, ECE Department, Sri Ramakrishna Institute of Technology, Coimbatore, Tamil Nadu, India
Online published on 14 February, 2017.
Addition is the basic arithmetic operation that has universal application in the fields of science and technology. Full adders play a vital role in the design of such arithmetic units and form the important contributor of power, speed and area. In this paper, performance of full adder structures based on Static CMOS, BBL PT, SRCPL, DPL, Hybrid logic and alternate adder structures 1 and 2 are analysed for deep sub-micron operation. This paper also proposes a new full adder structure constructed entirely using 2: 1 multiplexers which is found to exhibit superior performance characteristics at a much scaled down process technology of 32nm PTM with a supply voltage of 1V. Though, BBL PT adder is 23.2% faster than the proposed adder, the latter is 84% power efficient, has 80% better power delay product than the former and is smaller compared to all the adder structures under consideration. The proposed adder is 18.4% power efficient and 95.68% faster than static CMOs adder and 24.3% power efficient and 90.4% faster than alternate 2 adder structure.
low power, pass transistor, logic style, adder
