Design of Accumulate Compare and Select Unit of Viterbi Decoder at Reduced CMOS Process Technology

Wireless communication systems use convolutional codes to establish information transmission at high data rates. For decoding convolutional codes, Viterbi decoder based on the maximum likelihood decoding Viterbi algorithm is used. VLSI implementation of the Viterbi decoder consists of design of several functional units like Transition Metric Unit(TMU), Accumulate Compare and Select Unit(ACSU), Branch Metric Unit(BMU), Survivor Memory Unit and Path Metric Unit. In this paper, an alternate design for Accumulate Compare and Select Unit that employs Radix-2 and Radix-4 algorithms is proposed. The alternate design includes the use of subtractor and modified comparator unit built using multiplexers, in place of the comparator that performs the compare operation in the ACS Unit. The Radix-2 and Radix-4 ACSUs constructed using modified comparators is found to be 32.73% and 39.3% power efficient than those built using subtractors. Also, the Radix-4 ACSU with modified comparator is 39.6% faster than its counterpart built using subtractor.