Low Power VLSI Schematic Design of PC/BPSC Generation and Degeneration

Phase Code (PC) or Bi-Phase Space Code (BPSC) can be used as Line Coding Techniques. This paper deals with a coding system which can perform code generation and degeneration of both PC and BPSC schemes. The system is designed with 180nm technology with 53 number of transistors.. Power requirement is reduced by around 15%. The area requirement is 1482μ m2. The proposed system can be operated up to 500MHz.