A High Speed VLSI Architecture of a Pipelined Reed Solomon Encoder for Data Storage in Communication Systems

21st century is an era of wireless world. The cause of the current trend for wireless applications is the improved data rate for multifarious applications of communication. But during communication, the data might be distorted due to impairments of channels. Reduction of error due to noisy channels becomes critical. Novel high speed VLSI architecture for encoding Reed Solomon codes are presented in this paper. Pipelining and parallelizing allows inputs to be transmitted at high rates within minimum delay. The speed bottleneck in the basic LFSR based Reed Solomon encoder is eliminated by proposing a new modification of the LFSR into the form of an Infinite Impulse Response (IIR) filter. The proposed architecture results in critical path with less hardware overhead. An example illustrating the parallel and pipelined architecture of an encoder is given for (15, 9) RS code. The proposed architecture produces a delay of 2.33nS and its speed is of 428.27MHz.