*Assistant Professor, Department of EIE, J. J. College of Engineering and Technology, Trichy, India
**Assistant Professor, Department of EEE, Thiagarajar College of Engineering, Madurai, India
Online published on 14 February, 2017.
In this paper a new model 11 level inverter topology with minimum number of power electronic switches is introduced. In this proposed inverter circuit is controlled by the Sine Pulse Width Modulation [SPWM] technique and verified by MATLAB/Simulink software. The result is verified and also compared with various SPWM techniques in terms of Total Harmonic Distortion (THD) rate. Also prototype based experimental setup is developed and this inverter is controlled through Field Programmable Gate Array (FPGA). FPGA scheme can be easily extended to an n-level inverter.
Multilevel inverter, SPWM, MATLAB, THD, FPGA, Xilinx
