*Department of ECE, SNS College of Technology, Coimbatore, India
**Principal, SNS College of Technology, India
***Department of ECE, SNS College of Technology, Coimbatore, India
Online published on 14 February, 2017.
A new technique for test pattern generation (TPG) in a built-in self-test (BIST) environs is proposed here. The TPG customs the characteristic information of the circuit to generate the test vectors internally. The distinctive information of the circuit is extracted using recognized spectral techniques. The algorithm was tested on dissimilar counter circuits and performs extremely well compared to the random test patterns by ATALANTA. The hardware essential for the TPG in the counter circuit is the identical irrespective of the size of the counter. Thus the area overhead is nominal for greater size counter circuits.
DATPG, Fault Simulation, Fault Diagnosis
