Performance Analysis of an Efficient Architecture for Interference detector in Cognitive Radio Networks

The spectrum utilization is improved by cognitive radio (CR) as a promising technology. This technology allows unlicenced users to use the spectrum of the licenced users through sharing the same communication channel between them. The interference is occurred in spectrum due to the common channel utilization. Conventional methods for interference detection are based on the single hop communication and it does not support multi hop communication. Hence, this paper proposes efficient low power architecture of interference detector for CR networks. The proposed architecture is designed using Verilog HDL and synthesized using Xilinx Project Navigator. The performance of the proposed interference detection architecture is analyzed interms of power and current consumption on various spartan 3E FPGA devives.