An Improved Finite Impulse Response Filter Architecture using Substrate Bias Logic for Low-Power Applications

Substrate bias logic (SBL) complementary metal oxide semiconductor (CMOS) model is extended to logic gates and is used for the implementation of adders, multipliers and flip-flops required for finite impulse response (FIR) filter. The power efficiency of FIR filter has been calculated and compared using both static CMOS and SBL CMOS models. It was found that power dissipation can be significantly reduced by 30% for the supply voltage of 1.2 V using SBL CMOS model as compared to static CMOS model. The leakage power can be reduced by incorporating LECTOR logic with SBL technique. The filter design using SBL CMOS model can be used in developing digital signal processing (DSP) systems for portable multimedia devices.