Reducing Energy Consumption by Code Repositioning for Memory Levels

The valuable time of the core processor is lost for fetching the data to/from memory, when attached to relatively slow memory devices and this issue is termed as Memory Wall problem. In this regard, system designed for specific applications like embedded system performance can be improved, when it is upgraded by adding a tiny, fast cum energy efficient on-chip SRAM scratchpad memory(SPM). The main objective is to lessen the memory wall problem and to minimize the energy consumption by optimizing the code object during memory access time. Most of the recent works addressed on memory wall problem dealt with either on-chip or off-chip memory and quite a few works focused on optimizing both. In this paper, performance of three different memory architecture models namely SPM-alone, cache-alone and combination of both SPM-with-cache model is estimated and it is found that SPM-with-cache model is preferable for most complex applications. A two stage meta heuristic based strategy involving partial enumeration technique and Tabu search is implemented in this work for the estimation of the energy consumption and it is observed that system with combined SPM-with-cache consumes relatively less energy than the system with only either of them for complex instruction.