Asian Journal of Research in Social Sciences and Humanities

The spilt radix Fast Fourier Transform (FFT) in signal and image processing they require low computational power. The main aspect to choose the algorithm and architecture is to implement the realization of a 3/6 FFT processor based on a pipeline architecture, also to analyze the area consumption and logical verification of 6 point radix 3/6 FFT algorithm. The special purpose FFT architecture has been developed for analyzing the respective computational area that consumes in FPGA. The proposed algorithm is the combination of radix-3 and radix-6 FFT. It is a variant of split radix and it is flexibly implemented of length 2^r x 3^m DFT. The novel order permutation of sub-DFTs and reduction of the number of arithmetic operations enhance the practicability of the proposed algorithm.