Circuit Design & Simulation Lab. Department of Physics & Electronics, Dr. R.M.L. Avadh University, Faizabad (U.P.), India
*E-mail: rktiwari2323@yahoo.co.in
Online published on 11 January, 2013.
The parasitic capacitance circuit has wide application in analog and digital circuit design. Proper selection of device model has been playing an important role in the design parasitic capacitance circuit. Present paper focuses a critical analysis of frequency response of BJT, FET and nMOS parasitic capacitance circuit by varying input capacitance and obtained gain and bandwidth by varying frequency for 10 Hz to 100 GHz. All the simulation has been performed using SPICE tool and optimized the device parameter.
Parasitic capacitance, BJT, FET, nMOS, Frequency response, Simulation
