Dynamically Programmable Cache for Multimedia Applications

The demand for higher computational power is ever increasing, and hence, the computational resources on chip. To keep us with this increase, the size of the onchip cache memory has also been consistently increasing. While some applications utilize the silicon real-state on chip, most application, especially multimedia and signal processing applications do not utilize the on-chip cache memory efficiently. This is because multimedia and signal processing applications data are not highly referenced. This paper shows novel cache architecture that utilizes the silicon real-state and increase performance of multimedia and signal processing applications. The main idea is to interleave Filed Programmable Cache Arrays (FPGAs) between data cache lines and use these added computational cells to execute some subroutines in the cache. Thus instead of juggling the data in and out of the cache, DPC allows algorithms to execute data while in the D-cache. The added FPGA will utilize the cache more, reduce memory bottleneck, and increase performance. The new architecture is called Dynamically Programmable Cache (DPC). DPC can function as a conventional Data cache, algorithm accelerator, or a combination of the two. This paper shows DPC machine having 5X the speedup over Altera FLEX10K and 2X the speed over high speed General Purpose Processors such as ULTRA SPARC II for some multimedia application.