An Effective Asynchronous Micropipeline using Double Edge Triggered D Flipflop

This paper presents the design and simulation results of asynchronous micro pipeline using an effective Double Edge Triggered D Flip-Flop (DETDFF). Here an attempt has been made to construct an asynchronous micro pipeline using the proposed DETDFF with an aim to have low power consumption and delay. The performance of the proposed circuit in terms of Power consumption and delay is compared with Asynchronous Micropipelines constructed using other DETDFFs. The circuits were simulated using TSPICE in both 0.18μ and 0.13μ CMOS technologies for an operating frequency of 1Ghz. The simulation results shows that the micropipeline desined using the proposed DETDFF consumes low power and has lower delay.