Domino logic circuit with reduced leakage and improved noise margin

As the technology is continuously scaled, leakage currents become a major contributor to the total power dissipation. A reduction in power supply voltage is necessary to reduce dynamic power and avoid reliability problems in deep sub-micron (DSM) regimes. Threshold voltage reduction accompanies supply voltage scaling to maintain the performance, but it exponentially increases the subthreshold leakage currents. Domino logic circuits are extensively used in high performance microprocessors due to their superior speed and area characteristics compared to static CMOS circuits. But they are extremely susceptible to noise and are highly leaky. In this paper, to the standard low-Vth domino logic, an additional control circuit referred as Adaptive Voltage Level (AVL) circuit is used which reduces the voltage fed to the load circuit in order to reduce the leakage power. This technique provides a lesser leakage power and evaluation delay than low- Vth technique. Simulation results revealed that the data dependent leakage is less here when compared to low-Vth and dual-Vth techniques. The noise margin is much improved compared to dual-Vth but at the slight expense of evaluation delay. This technique can be used as an alternative to dual-Vth technique in noisy environments.