The cache memories are an important part of a typical memory hierarchy. They help to match the fast processor, with a slower secondary memory, which acts as a bottleneck for high speed computing. The DRAM, another important memory, with its small, one transistor cell, looks very tempting to be used as cache memory but it has not been able to replace the SRAM because of the complex process steps and hence a resulting increase in the manufacturing cost. The challenge is to minimize the leakage power in the SRAM as it has to retain the data for some time, independent of the access period, hence cannot be shut off completely. This paper introduces a new transmission gate based SRAM cell. A comparison of this cell has been made with the recently proposed single ended write assist cell. The basis of comparison has been parameters such as static noise margin (SNM), which gives a good indication of the read and write stability, other parameters are power dissipation, write time, precharge voltage window, and threshold mismatch. This paper uses the differential sense amplifier, and as the cells discussed in this paper are single ended, this results in twice the number of cells being connected to the same sense amplifier resulting in a reduction in the area. Results have been obtained using the IBM 130nm Mosfet model parameters.
Cache memory, bit line, word line, (SNM) static noise margin, leakage power, sense amplifier
