Design and Performance Verification of Cache RAM

This present the design of a L3 (level-3) cache Random Access Memory (RAM). paper has described last level cache memory structure, which is designed mainly to improve the timing, reduce the power consumption and better performance. Functional verification as well as pre layout and post layout STA (Static Timing Verification) and ERC (Electric Rule Check) verifications are done on the 3MB cache. The cache hierarchy design in existing SMT (Simultaneous Multi Threading) and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 (level-1) data cache did not scale over the Past decade. Instead, larger unified L2 (level-2) and L3 caches were introduced. SDP (Structural Data Path) methodology is better than the RLS (RTL to Logic Syntheses) methodology for data path configurations. Simulation results are reported in support of the design and also presented the verification results.