In this paper various multiplier architectures are compared in terms of dissipated energy, propagation delay, and area occupation, in view of lowpower low-voltage signal processing for low-frequency applications. It is mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Due to shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 W/MHz versus 9.6 W/MHz for 0.18μm CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 W/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency. The reduced number of Vdd-to-ground paths also contributes to a significant decrease of static consumption.
