International Journal of Advanced Research in Engineering and Applied Sciences
  • Year: 2016
  • Volume: 5
  • Issue: 5

Comparative study of arithmetic & logic units on FPGAs

  • Author:
  • Harshit Shrivastava, Himanshu Nautiyal, Sangeeta Shukla
  • Total Page Count: 9
  • Page Number: 1 to 9

*Department of Electronics & Communication Engineering, Sagar Institute of Research & Technology, Bhopal

**Department of Electronics & Communication Engineering, Sagar Institute of Research & Technology, Bhopal

***Department of Electronics & Communication Engineering, Sagar Institute of Research & Technology, Bhopal

Online published on 1 August, 2018.

Abstract

This paper deals with low power ALU design and its implementation Spartan 3 FPGA. Most of power is consumed in ALU in any processor and hence reduction in ALU power is needed. In this work, two ALUs are designed; the first design is conventional with all the logic blocks running all the time, in second design only those blocks are active which are used by currently selected operation, rest all blocks are inactive. This reduces the dynamic power consumption of the design.

Keywords

ALU, Low Power, Dynamic Power, Blocked I/O, FPGA