Pipelined implementation of aes-128 encryption module on reconfigurable logic

This paper presents the hardware implementation of 128 bit AES encryption. The implementation is optimized in order to reduce delay. In order to reduce delay pipelined architecture is employed. Also sequential shifters in shift_row process are replaced by combinational shifters to increase maximum operating frequency. The target device is Virtex-5 XC5VLX50-2FF676 speed grade-2.