Automatic Generation of Interfaces between Incompatible Hardware Intellectual Properties (IPs) from Uml Models

The presented work deals with automatic interfaces generation for incompatible hardware Intellectual properties (IPs) from UML models. Our aim is to provide Systems On Chips (SOCs) designers with an UML based environment for modelling, configuring incompatible IPs, and automatic generation of interface in a standard Hardware Description Language (HDL) like VHDL. In our case, each IP is modelled as an UML component with well defined interface including input and output signals and some attributes. The whole SOC is modelled via UML structure diagram. Memory timing constraints are modelled via UML timing diagrams. Communication protocols for incompatible IPs are modelled via statecharts with hierarchic and concurrent states. From these diagrams, a Finite State Machine with Data path (FSMD) for interface is generated automatically. The latter is then translated to a VHDL code.