Post Graduate Student, Electronics and Communication Engineering, Department of Electronics and Communication Engineering, Institute of Engineering and Industrial Technology, Malandighi, Durgapur-12, West Bengal, India
A carry look-ahead adder improves speed of addition because it can produce the final carry before the generation of final sum. In this work 4 bit & 8 bit CLA has been implemented using dynamic logic, Domino style and also compare the result in terms of average power consumption, propagation delay & power delay product with the help of TSPICE simulation tool considering feature size 150nm, 200nm & 250nm. Domino logic of 150 nm is more appropriate style to implement the CLA design as because average power consumption, propagation delay & power delay product is 210.01 uw, 0.06 ns, 12.59 p Joule respectively for 8 bit CLA which is more optimized than the output of other channel lengths. In this design the numbers of transistors required are 172 and 520 for 4 bit and 8 bit respectively. Result analysis also done for intrinsic and extrinsic load capacitance.
Domino Logic, Carry Look Ahead Adder, High Speed Adder, Dynamic Logic, 8 bit CLA, Low Power Adder, TSPICE, Optimized CLA Design, power dissipation
