Various Parametric Analysis and Comparison of Full Adder Cells for DSP Data Path Block

In this paper the main topologies of Conventional, 16T, 14T and 10T Full Adder cells are analyzed with speed, power consumption, and power-delay product parameters. The comparison has been performed on three classes of circuits, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a T-spice, also including the parasitic derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. Minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS Transistors.