FPGA Implementation of Biometric EVM using AADHAAR Authentication

It has been uphill for the election commission to conduct free and trustful selection of representatives is considered as biggest democratic country like India. Even then EC has to spend handsome amount on storage, security and updating with technology. This proposed EVM illustrate the idea to strengthen and digitalize the present technology EVM by using AADHAR authentication and biometric. Proposed system will forged and count votes with higher convenience and potency, even build the electoral procedures easy and bring up accuracy ratio of ballot examination just by replacing with FPGA using Verilog HDL. Voter identification process is reduced by introducing biometric based voting. That allows voters to verify their identity and authorizes them to cast vote. The counting of votes are done mechanically so time are reduced and result are often declared in less unit of time. The improvisations aim at increasing the protection, flexibility, dependability, measurability in the present system. The modified system is lightweight, configurability and reusability of FPGA have created it an appropriate alternative for planned design. Xilinx ISE Design Suite 14.7 Version and Arduino Uno are used for simulation and implementation of design.