Analysis of Cache-Coherence protocols for Multi-Core Architectures

With the single-core processors it is very difficult to speedup processors by increasing frequency due to overheat and high power consumption. Multi-core architectures came to existence to speedup the application performance by distributing workload to each core. Multi-core architectures are emerging as a new business trend for single-core processors to reach the maximum performance. Moreover, these architectures are also designed for exploiting thread-level parallelism by using OpenMP (Open Multi-Processing) and Pthreads (POSIX Threads). However, the use of shared caches in a multiprocessor system causes data inconsistency problems. This paper mainly focuses on the analysis of cache coherence protocols to avoid inconsistency in case of shared cache and the parallelization of Pthreads for multi-core architectures.