Minimization of Test Vectors for Combinational Circuits using ILP and DFT Tools

Design For Test is a method to merge design and testing process which helps in improvising the test coverage and test minimization and thereby reducing the testing cost for complex digital designs. This paper presents an effective method to enhance test coverage of various complex combinational circuits. This work deals with two phases. In the first phase, Scan insertion is done. In the second phase, compact test patterns are generated along with ATPG effectiveness, test coverage using FAST SCAN. The test patterns are generated in chain, serial and parallel formats. There are many optimization techniques used to minimize the test patterns among them Zero One Linear programming (ZOLP) is one. It uses Duality theory for fault set identification and test minimization. In this paper these two methodologies are used and compared for their effective test coverage and CPU processing time.