Automatic Clock Generator Model for VLSI Application A Machine-Intelligence based approach

In order to meet modern complex VLSI applications the clock plays very important role. Since whole set of activities are dependent on clocks that are required for several modules in architecture of a digital integrated-circuits. There are two aspects of designing that deals with clock while designing a VLSI chip, clock-generation and clock-distribution. There are mature methodologies & several smart-EDA tools available to intelligently resolve clock-distribution issue for most complex integrated circuits. However, over many years, designing a block for clock generation has been very much manual process that is done by engineers with little support available from tools. This paper presents a machineintelligence based software tool that can strengthen the engineers in clock-generation design modules. Where HDL based smart (hierarchical) models are automatically generated upon understanding specific aspects of required clock-circuitry.