1Department of Electronics, J.D.C.O.E.M, RTMNU, Nagpur
2Vice principal, C.I.C.O.E.T., Nagpur
Online published on 27 June, 2017.
This paper proposes new method to combine Rijndael encryption and decryption algorithm implementation on FPGA to reduce area and high throughput. This AES algorithm runs its symmetric cipher algorithm using encrypt/decrypt block and key size of 128 bits. The proposed architecture would be implemented by using Verilog HDL and synthesized, placed and routed in Spartan 3A using Xilinx Family and hardware implementation on DE2,cyclone II FPGA.
AES, FPGA, cipher, throughput, Verilog HDL
