Department of P.G.Studies & Research in Electronics, Mangalore University, Mangalore, Karnataka (India)
Online published on 27 June, 2017.
This paper reports a study on logic equation (any) and its simplification process by writing the program on the basis of truth table with respect to given parameters. The program for the logic equation is written using Verilog/VHDL and then synthesize and implementing the program is carried out. Timing diagram on Schematic FPGA results are obtained on Spartan-3 FPGA using Xilinx simulation software.
Verilog, integrated circuit, medical imaging, broadband, Spartan
