1Professor, MTECH scholar, RGM College of Engineering and Technology, Nandyal
2Assoc. professor, MTECH scholar, RGM College of Engineering and Technology, Nandyal
3MTECH scholar, RGM College of Engineering and Technology, Nandyal
Online published on 27 June, 2017.
This paper proposes a new comparator design feature wide-range and high-speed operation using only straight digital CMOS cells. This comparator exploit a novel scalable parallel prefix structure that leverages the comparison outcome of the most significant bit, arranged bitwise toward the least significant bit only when the compared bits are equal. This method reduces active power indulgence by eliminate avoidable transitions in a parallel prefix structure that generate the N-bit comparison result after [log4 N] + [log16 N] + 4 CMOS gate delays. This comparator is collected of close by interconnected CMOS gates with a maximum fan-in and fan-out of five and four, correspondingly, free of the comparator bit width. The main advantages of this design are high speed and power competence, maintain over a extensive range. in addition, this design uses a ordinary reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth. We are designed scalable digital CMOS Comparator using a parallel prefix tree in MICROWINDtool and analyzed in 180nm, 120nm, 65nm technologies at different supply voltages in terms of power,area,delay and power delay product.
High-speed mathematics, high-speed wide-bit comparator structural design, parallel prefix tree structure
