This paper presents a proposed architecture for PCI Express Physical Link Layer Receive Logic. The design contains all necessary features required for the implementation of the PCIe Physical Link Layer Protocol for X4 Link connection. The physical layer receive logic buffers data taken from the link, decodes it to make it readable for the higher layers. This design is intended for FPGA implementation of PCIe for VIRTEX series devices.
Byte unstripping Descrambler, 8b/10b decoder Register Transfer Logic (RTL) Data link layer packet (DLLP), Transaction layer packet (TLP)
