Carry Select Adder (CSLA) is the fastest digital adder when compared with any other former adders. Adder is a basic block which is used in many DSP processors to perform all arithmetic operations. There is a scope in reduction of area and power of CSLA. By using a simple gate level modification, square root CSLA (SQRT CSLA) was developed and implemented. In this paper, the new architecture of CSLA is proposed which reduces area and power further as compared to SQRT CSLA without affecting the delay. The performance of the proposed design is evaluated in terms of Delay and Area with logical effort. The results are compared and tabulated to establish that, the new CSLA is better as compared with SQRT CSLA.
Area efficient, SQRT CSLA, New CSLA architecture, SCLB, DIDO
