Department of Electronics and Communication Engineering, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India
Online published on 27 June, 2017.
This paper presents the design and evaluation of two new processing elements for reconfigurable computing. A novel single-precision floating point processing element (FPPE) using a 24-b variant of the proposed data paths is also presented. Comparison with competing architectures shows that the FPPE provides two orders of magnitude higher throughput. Furthermore, to evaluate its feasibility as a soft-processing solution, we also map the floating point unit onto the Vertex 4 and 5 devices. When compared against popular field-programmable-gatearray-based floating point units, our design on Vertex 5 showed significantly lower resource utilization, while achieving comparable peak operating frequency.
Computer arithmetic, data path design, reconfigurable computing
