Power Aware Test Data Compression Schemes for Scan-based Testing

Increasing test data volume and power dissipation during scan testing are two major issues faced bythe semiconductor industry. Hightest volume increases the testing time and may also exceed the tester'smemory capacity. This will result in the need of multiple reloads of the test data to the tester memory which increases testing time and test cost substantially. High power can cause structural damage to silicon, bonding wire or to the package. To decrease test data volume and power, a number of test data compression methods and low-power testing schemes have been presented in the literature. This paper explores run-length based compression methods to reduce test data volume and X filling techniques to reduce power dissipation. Experiments carried out on ISCAS 89 benchmark circuits’ shows VPDRL compression technique combined with MT filling gives better compression ratio and red uced power dissipation as compared to other compression and fill techniques analyzed.